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<div class="title">Intrinsic Functions for CPU Instructions</div>  </div>
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<table class="memberdecls">
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#gac71fad9f0a91980fecafcb450ee0a63e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gad3efec76c3bfa2b8528ded530386c563"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#ga3c34da7eb16496ae2668a5b95fa441e7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#ga93c09b4709394d81977300d5f84950e5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#gacb2a8ca6eae1ba4b31161578b720c199"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#gab1c9b393641dc2d397b3408fdbe72b96"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#ga4717abc17af5ba29b1e4c055e0a0d9b8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a> (uint32_t value)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gaeef6f853b6df3a365c838ee5b49a7a26"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">__REVSH</a> (int32_t value)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order in signed short value.  <a href="#ga1ec006e6d79063363cb0c2a2e0b3adbe"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value [not for Cortex-M0 variants].  <a href="#gad6f9f297f6b91a995ee199fbc796b863"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a> (uint32_t value, uint32_t shift)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate a value right by a number of bits.  <a href="#gaf66beb577bb9d90424c3d1d7f684c024"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a> (volatile uint8_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (8 bit) [not for Cortex-M0 variants].  <a href="#ga9e3ac13d8dcf4331176b624cf6234a7e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a> (volatile uint16_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (16 bit) [not for Cortex-M0 variants].  <a href="#ga9feffc093d6f68b120d592a7a0d45a15"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a> (volatile uint32_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (32 bit) [not for Cortex-M0 variants].  <a href="#gabd78840a0f2464905b7cec791ebc6a4c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a> (uint8_t value, volatile uint8_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (8 bit) [not for Cortex-M0 variants].  <a href="#gaab6482d1f59f59e2b6b7efc1af391c99"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a> (uint16_t value, volatile uint16_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (16 bit) [not for Cortex-M0 variants].  <a href="#ga0a354bdf71caa52f081a4a54e84c8d2a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> (uint32_t value, volatile uint32_t *addr)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (32 bit) [not for Cortex-M0 variants].  <a href="#ga335deaaa7991490e1450cb7d1e4c5197"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> (void)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Remove the exclusive lock [not for Cortex-M0 variants].  <a href="#ga354c5ac8870cc3dfb823367af9c4b412"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">__SSAT</a> (unint32_t value, uint32_t sat)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Signed Saturate [not for Cortex-M0 variants].  <a href="#ga7d9dddda18805abbf51ac21c639845e1"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">__USAT</a> (uint32_t value, uint32_t sat)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsigned Saturate [not for Cortex-M0 variants].  <a href="#ga76bbe4374a5912362866cdc1ded4064a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros [not for Cortex-M0 variants].  <a href="#ga90884c591ac5d73d6069334eba9d6c02"></a><br/></td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Description</h2>
<p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. </p>
<hr/><h2>Function Documentation</h2>
<a class="anchor" id="ga354c5ac8870cc3dfb823367af9c4b412"></a><!-- doxytag: member="Ref_cmInstr.txt::__CLREX" ref="ga354c5ac8870cc3dfb823367af9c4b412" args="(void)" -->
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        <tr>
          <td class="memname">void __CLREX </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<div class="memdoc">
<p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0 variants]. </p>

</div>
</div>
<a class="anchor" id="ga90884c591ac5d73d6069334eba9d6c02"></a><!-- doxytag: member="Ref_cmInstr.txt::__CLZ" ref="ga90884c591ac5d73d6069334eba9d6c02" args="(uint32_t value)" -->
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          <td class="memname">uint8_t __CLZ </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function counts the number of leading zeros of a data value [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>number of leading zeros in value </dd></dl>

</div>
</div>
<a class="anchor" id="gab1c9b393641dc2d397b3408fdbe72b96"></a><!-- doxytag: member="Ref_cmInstr.txt::__DMB" ref="gab1c9b393641dc2d397b3408fdbe72b96" args="(void)" -->
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        <tr>
          <td class="memname">void __DMB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>

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<a class="anchor" id="gacb2a8ca6eae1ba4b31161578b720c199"></a><!-- doxytag: member="Ref_cmInstr.txt::__DSB" ref="gacb2a8ca6eae1ba4b31161578b720c199" args="(void)" -->
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          <td class="memname">void __DSB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>

</div>
</div>
<a class="anchor" id="ga93c09b4709394d81977300d5f84950e5"></a><!-- doxytag: member="Ref_cmInstr.txt::__ISB" ref="ga93c09b4709394d81977300d5f84950e5" args="(void)" -->
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          <td class="memname">void __ISB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>

</div>
</div>
<a class="anchor" id="ga9e3ac13d8dcf4331176b624cf6234a7e"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXB" ref="ga9e3ac13d8dcf4331176b624cf6234a7e" args="(volatile uint8_t *addr)" -->
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      <table class="memname">
        <tr>
          <td class="memname">uint8_t __LDREXB </td>
          <td>(</td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive LDR command for 8 bit value [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint8_t at (*addr) </dd></dl>

</div>
</div>
<a class="anchor" id="ga9feffc093d6f68b120d592a7a0d45a15"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXH" ref="ga9feffc093d6f68b120d592a7a0d45a15" args="(volatile uint16_t *addr)" -->
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      <table class="memname">
        <tr>
          <td class="memname">uint16_t __LDREXH </td>
          <td>(</td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive LDR command for 16 bit values [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint16_t at (*addr) </dd></dl>

</div>
</div>
<a class="anchor" id="gabd78840a0f2464905b7cec791ebc6a4c"></a><!-- doxytag: member="Ref_cmInstr.txt::__LDREXW" ref="gabd78840a0f2464905b7cec791ebc6a4c" args="(volatile uint32_t *addr)" -->
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        <tr>
          <td class="memname">uint32_t __LDREXW </td>
          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive LDR command for 32 bit values [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>value of type uint32_t at (*addr) </dd></dl>

</div>
</div>
<a class="anchor" id="gac71fad9f0a91980fecafcb450ee0a63e"></a><!-- doxytag: member="Ref_cmInstr.txt::__NOP" ref="gac71fad9f0a91980fecafcb450ee0a63e" args="(void)" -->
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      <table class="memname">
        <tr>
          <td class="memname">void __NOP </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<div class="memdoc">
<p>This function does nothing. This instruction can be used for code alignment purposes. </p>

</div>
</div>
<a class="anchor" id="gad6f9f297f6b91a995ee199fbc796b863"></a><!-- doxytag: member="Ref_cmInstr.txt::__RBIT" ref="gad6f9f297f6b91a995ee199fbc796b863" args="(uint32_t value)" -->
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          <td class="memname">uint32_t __RBIT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<div class="memdoc">
<p>This function reverses the bit order of the given value [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>

</div>
</div>
<a class="anchor" id="ga4717abc17af5ba29b1e4c055e0a0d9b8"></a><!-- doxytag: member="Ref_cmInstr.txt::__REV" ref="ga4717abc17af5ba29b1e4c055e0a0d9b8" args="(uint32_t value)" -->
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      <table class="memname">
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          <td class="memname">uint32_t __REV </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function reverses the byte order in integer value.</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>

</div>
</div>
<a class="anchor" id="gaeef6f853b6df3a365c838ee5b49a7a26"></a><!-- doxytag: member="Ref_cmInstr.txt::__REV16" ref="gaeef6f853b6df3a365c838ee5b49a7a26" args="(uint32_t value)" -->
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        <tr>
          <td class="memname">uint32_t __REV16 </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function reverses the byte order in two unsigned short values.</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>

</div>
</div>
<a class="anchor" id="ga1ec006e6d79063363cb0c2a2e0b3adbe"></a><!-- doxytag: member="Ref_cmInstr.txt::__REVSH" ref="ga1ec006e6d79063363cb0c2a2e0b3adbe" args="(int32_t value)" -->
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        <tr>
          <td class="memname">int32_t __REVSH </td>
          <td>(</td>
          <td class="paramtype">int32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function reverses the byte order in a signed short value with sign extension to integer.</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Reversed value </dd></dl>

</div>
</div>
<a class="anchor" id="gaf66beb577bb9d90424c3d1d7f684c024"></a><!-- doxytag: member="Ref_cmInstr.txt::__ROR" ref="gaf66beb577bb9d90424c3d1d7f684c024" args="(uint32_t value, uint32_t shift)" -->
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t __ROR </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>shift</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function rotates a value right by a specified number of bits.</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be shifted right </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">shift</td><td>Number of bits in the range [1..31] </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Rotated value </dd></dl>

</div>
</div>
<a class="anchor" id="ga3c34da7eb16496ae2668a5b95fa441e7"></a><!-- doxytag: member="Ref_cmInstr.txt::__SEV" ref="ga3c34da7eb16496ae2668a5b95fa441e7" args="(void)" -->
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          <td class="memname">void __SEV </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>

</div>
</div>
<a class="anchor" id="ga7d9dddda18805abbf51ac21c639845e1"></a><!-- doxytag: member="Ref_cmInstr.txt::__SSAT" ref="ga7d9dddda18805abbf51ac21c639845e1" args="(unint32_t value, uint32_t sat)" -->
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          <td class="memname">uint32_t __SSAT </td>
          <td>(</td>
          <td class="paramtype">unint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>sat</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function saturates a signed value [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [1..32] </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Saturated value </dd></dl>

</div>
</div>
<a class="anchor" id="gaab6482d1f59f59e2b6b7efc1af391c99"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXB" ref="gaab6482d1f59f59e2b6b7efc1af391c99" args="(uint8_t value, volatile uint8_t *addr)" -->
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          <td class="memname">uint32_t __STREXB </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive STR command for 8 bit values [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

</div>
</div>
<a class="anchor" id="ga0a354bdf71caa52f081a4a54e84c8d2a"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXH" ref="ga0a354bdf71caa52f081a4a54e84c8d2a" args="(uint16_t value, volatile uint16_t *addr)" -->
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          <td class="memname">uint32_t __STREXH </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive STR command for 16 bit values [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

</div>
</div>
<a class="anchor" id="ga335deaaa7991490e1450cb7d1e4c5197"></a><!-- doxytag: member="Ref_cmInstr.txt::__STREXW" ref="ga335deaaa7991490e1450cb7d1e4c5197" args="(uint32_t value, volatile uint32_t *addr)" -->
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          <td class="memname">uint32_t __STREXW </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function performs a exclusive STR command for 32 bit values [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

</div>
</div>
<a class="anchor" id="ga76bbe4374a5912362866cdc1ded4064a"></a><!-- doxytag: member="Ref_cmInstr.txt::__USAT" ref="ga76bbe4374a5912362866cdc1ded4064a" args="(uint32_t value, uint32_t sat)" -->
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          <td class="memname">uint32_t __USAT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>sat</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>This function saturates an unsigned value [not for Cortex-M0 variants].</p>
<dl><dt><b>Parameters:</b></dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [0..31] </td></tr>
  </table>
  </dd>
</dl>
<dl class="return"><dt><b>Returns:</b></dt><dd>Saturated value </dd></dl>

</div>
</div>
<a class="anchor" id="gad3efec76c3bfa2b8528ded530386c563"></a><!-- doxytag: member="Ref_cmInstr.txt::__WFE" ref="gad3efec76c3bfa2b8528ded530386c563" args="(void)" -->
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          <td class="memname">void __WFE </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p>
<ul>
<li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul>
<li>An exception, unless masked by the exception mask registers or the current priority level.</li>
<li>An exception enters the Pending state, if SEVONPEND in the System Control Register is set.</li>
<li>A Debug Entry request, if Debug is enabled.</li>
<li>An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.</li>
</ul>
</li>
</ul>
<ul>
<li>If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately. </li>
</ul>

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</div>
<a class="anchor" id="gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a><!-- doxytag: member="Ref_cmInstr.txt::__WFI" ref="gaed91dfbf3d7d7b7fba8d912fcbeaad88" args="(void)" -->
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          <td class="memname">void __WFI </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div>
<div class="memdoc">
<p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p>
<ul>
<li>A non-masked interrupt occurs and is taken.</li>
<li>An interrupt masked by PRIMASK becomes pending.</li>
<li>A Debug Entry request. </li>
</ul>

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